Use of Cadence Tools for Design and Layout of a Charge Sharing Measurement Circuit in a 90nm CMOS Process

By Oluwole Amusan Introduction Charge sharing is due to multiple node charge collection from a single ion strike. Charge sharing was first observed in SRAM designs [1], and recent work [2] – [6] has shown charge sharing to be a major Single Event Effect (SEE) for deep-submicron technologies due to the reduced spacing of circuit…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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Silicon Ensemble Tutorial – written by Philippe Adell

Silicon Ensemble Tutorial – written by Philippe Adell   The objective of this tutorial is to provide insight on how to use Cadence tools to design an application specific digital integrated circuit. This tutorial details the steps that have been followed to obtain the layout and schematic of a digital circuit (~2500 gates) from a…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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Cadence Manual for Vanderbilt Students and Faculty User Setup and Basic Tutorial

A Cadence University Program Member Version 4.46 Department of Electrical Engineering and Computer Science Vanderbilt University By Jeff Kauppila j.kauppila@vanderbilt.edu Table of Contents 1. Getting Started First Time User Return User 2. Simple Tutorial 3. Advanced Tutorial Disclaimer: Information is provided “as is” without warranty of guarantee of any kind. No statement is made and…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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Cadence Overview

Cadence Overview Often, it is difficult for a new user to understand the relationship between all of the different tools provided by Cadence. Here we will try to describe and document the different tools we use. We will update this as we learn more about the different tools. Send a message to one of the…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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2010 research projects using Cadence tools

2010 Research Projects: Corey Toomey’s use of cadence tools for statistical fault injection at the register transfer level . Ray Blaine’s use of cadence tools to create the SNACC layout technique for analog circuits.    

Posted by Barry Templeton on August 21, 2012 in , Cadence

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2009 research projects using Cadence tools

2009 Research Projects: Matt Gadlage’s Single-Event Transient Pulse Measurement Circuit in a 65 nm CMOS process designed using Cadence tools. Sarah Armstrongs’s SerDes device for single-event error characterization simulated using Cadence tools.  

Posted by Barry Templeton on August 21, 2012 in , Cadence

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2008 research projects using Cadence tools

2008 Research Projects: Pierre Maillard’s Delay-Locked Loop mixed-signal circuits designed using Cadence tools. Brian Olson’s RHBD Switched-Capacitor Comparator test circuit designed using Cadence tools.    

Posted by Barry Templeton on August 21, 2012 in , Cadence

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Cadence Project Examples

This page describes some of the research projects that are using the Cadence tools for layout and simulation   Andrew Kelly Cadence has been used to design Switched Capacitor (SC) networks for Sample and Hold (S/H) differential amplifier input applications. Schematic designs are being used to determine the effectiveness of the amplifier in mitigating Single…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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2007 research projects using Cadence tools

2007 Research Projects: Oluwole Amusan’s charge sharing test circuit designed using Cadence tools. Daniel Loveless’ Phase-Locked Loop mixed signal circuits designed using Cadence tools.  

Posted by Barry Templeton on August 21, 2012 in , Cadence

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2012 Cadence Usage in Study and Research Projects

2012 Cadence Use in the Classroom: The Cadence Custom IC Design Suite of tools is extensively used in the EECE 285 VLSI Design class.  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout,…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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