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UltraSim Tips & Tricks
Traditional SPICE Simulator UltraSim UltraSim Modes UltraSim Tips & Tricks
Posted by Barry Templeton on August 21, 2012 in , Cadence
UltraSim Modes
Traditional SPICE Simulator UltraSim UltraSim Modes UltraSim Tips & Tricks Mode Comparison
Posted by Barry Templeton on August 21, 2012 in , Cadence
2011 research on using Cadence UltraSim
Traditional SPICE Simulator UltraSim UltraSim Modes UltraSim Tips & Tricks
Posted by Barry Templeton on August 21, 2012 in , Cadence
A Hardened-by-Design Bias Circuit Utilizing Sensitive Node Active Charge Cancellation (SNACC)
R. W. Blaine, S. E. Armstrong, B. D. Olson, W. T. Holman, J. S. Kauppila, and L. W. Massengill I. Background Bias circuitry can be particularly sensitive to single events (SE). Previous work has shown that this phenomena can produce extreme circuit behaviors [1,2,3]. In these works this behavior manifested itself in three different ways:…
Posted by Barry Templeton on August 21, 2012 in , Cadence
USING CADENCE TOOLS FOR STATISTICAL FAULT INECTION AND ANALYSIS AT THE REGISTER TRANSFER LEVEL USING THE VERILOG PROCEDURAL INTERFACE
By Corey Toomey Introduction An approach has been developed to determine the architectural vulnerability factor of a design and its sub-modules along with other metrics including error latency and error persistence. The design used as a test bed for this thesis was an ASIC design with 1.1 million register elements. This design is written…
Posted by Barry Templeton on August 21, 2012 in , Cadence
Using Cadence to Simulate a SerDes Device for Single Event Error Characterization
Sarah Armstrong Introduction This effort is in collaboration with Boeing Space Systems Development group. Boeing designed a radiation-hardened by design (RHBD) Serializer-Deserializer (SerDes). Single-event transient simulations were performed on the full SerDes transmitter driver circuitry as well as specific circuit modules using the Cadence EDA tool suite with the Spectre circuit simulator. Single-Event Effect…
Posted by Barry Templeton on August 21, 2012 in , Cadence
Use of Cadence Tools for Design and Layout of an Single Event Transient (SET) Measurement Circuit in a 65-nm CMOS Process
By Matthew Gadlage Introduction A single event transient in a digital circuit can be induced by an energetic particle in combinational logic schematically located between storage cells. This transient can propagate through the combinational logic and arrive at the input of a latch on the latching edge of the clock. The wider…
Posted by Barry Templeton on August 21, 2012 in , Cadence
Use of Cadence Tools for Design and Layout of a Radiation-Hardened by Design Switched-Capacitor Comparator
By Brian Olson Introduction In modern integrated circuit processes, high-performance mixed-signal designs commonly use differential topologies and switched-capacitor input/feedback networks to obtain greater dynamic range, better noise rejection, and improved component matching to their single-ended, continuous-time counterparts [1]. For example, high-speed data converters make extensive use of differential switched-capacitor topologies. Unfortunately, switched-capacitor circuit topologies typically…
Posted by Barry Templeton on August 21, 2012 in , Cadence
Developing Mixed-Signal Delay Locked Loop Circuits in Cadence
By: Pierre Maillard The main goals of this project are to understand and quantify single-event transients (SET) in delay-locked loop (DLL) circuits and to develop radiation-hardened-by-design (RHBD) strategies for SET mitigation in DLLs. Using the Cadence software package we have developed we developed DLLs in 90 nm IBM technology. Fig. 1 illustrates the general block…
Posted by Barry Templeton on August 21, 2012 in , Cadence
Developing High-Speed Mixed-Signal Phase-Locked Loop Circuits in Cadence
By: Daniel Loveless The main goals of this project are to understand and quantify single-event transients (SET) in phase-locked loop (PLL) circuits and to develop radiation-hardened-by-design (RHBD) strategies for SET mitigation in PLLs. Using the Cadence software package we have developed numerous phase-locked loop topologies in 130 nm and 90 nm technology nodes. Fig. 1…
Posted by Barry Templeton on August 21, 2012 in , Cadence
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