2016 Research Projects Using Cadence Tools

2016 Cadence Use in the Classroom: The Cadence Custom IC Design Suite of tools is extensively used in the EECE 4385 VLSI Design class (Formerly EECE 285).  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all…

Posted by kauppijs on July 28, 2016 in , Cadence, Education, Training

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2015 Research Projects Using Cadence Tools

2015 Cadence Use in the Classroom: The Cadence Custom IC Design Suite of tools is extensively used in the EECE 285 VLSI Design class.  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout,…

Posted by kauppijs on July 27, 2015 in , Advanced Technologies, Cadence, Radiation Effects

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DCROs and FIR Design and Characterization

The goal of this project is to characterize single-event effects (SEEs) in All-Digital Phase-Locked Loops (ADPLLs) and develop radiation-hardening-by-design (RHBD) techniques against the error signatures. The Cadence EDA tool suite has been facilitating in this research in the following ways. Circuit schematic and layout design Cadence Virtuoso has been used for circuit schematic and layout…

Posted by kauppijs on August 1, 2014 in , Cadence, DCO, FIR

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2014 Research Projects Using Cadence Tools

2014 Cadence Use in the Classroom: The Cadence Custom IC Design Suite of tools is extensively used in the EECE 285 VLSI Design class.  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout,…

Posted by kauppijs on August 1, 2014 in , Advanced Technologies, Cadence, Radiation Effects

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Cadence Tool Use – Using Cadence Tools for RF Degraded Performance Model Development

Total Ionizing Dose (TID) causes parametric degradation in transistor DC parameters such as drain current (ID), small-signal transconductance (gm), which in turn causes degradation in transistor level RF parameters such as fT, fMAX and S-parameters. RF circuit performance depends on these parameters and hence would be affected by TID. The figure below shows the degradation…

Posted by kauppijs on July 29, 2013 in , Cadence

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Cadence Tool Use – Single-Event Transient Pulse-Width Measurement in Advanced CMOS Technologies

Semiconductor based systems utilized in a space environment are subject to a number of extreme environment effects including: Temperature extremes Operation in a vacuum Radiation environments A particular concern for the use of advanced CMOS technologies in space deals with the fact that ionizing particles incident on the semiconductor material cause information corruption and generate transient…

Posted by kauppijs on July 26, 2013 in , Cadence

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2013 Research Projects Using Cadence Tools

2013 Cadence Use in the Classroom: The Cadence Custom IC Design Suite of tools is extensively used in the EECE 285 VLSI Design class.  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout,…

Posted by kauppijs on July 26, 2013 in , BIST, Cadence, RF, SET, Single-Event

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Advanced Cadence Software Tutorial Part 5

Import/Export GDS/CIF Files Importing and exporting GDS or CIF files can be a difficult process to do successfully.  The steps of the process are rather simple, but getting the technology files and layers to correspond can be very difficult.  The University of California Berkeley has a great tutorial on Importing and Exporting GDS and CIF…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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Advanced Cadence Software Tutorial Part 4

Layout vs. Schematic The first step in running LVS is to make an extracted view from the layout you have just completed.  In this case, and in most cases, you need to extract with parasitic caps.  We discussed the extraction process in the first section of this tutorial, so we will not discuss it here.Next,…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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Advanced Cadence Software Tutorial Part 3

Layout Generation from a Schematic In this section, we will look at how to create a layout from a previously created schematic circuit design.  In the following session  Layout vs. Schematic, we will use a powerful tool in the Cadence package to compare our layout to our schematic.  This will allow us to be more…

Posted by Barry Templeton on August 21, 2012 in , Cadence

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