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Cadence Project Examples

This page describes some of the research projects that are using the Cadence tools for layout and simulation

Andrew Kelly

Cadence has been used to design Switched Capacitor (SC) networks for Sample and Hold (S/H) differential amplifier input applications. Schematic designs are being used to determine the effectiveness of the amplifier in mitigating Single Event Transients (SETs) induced in the input differential switch network via common mode rejection. Layout techniques modeled in TCAD convert SETs to a common mode signal and provide appropriate current pulses for the Cadence Spectre simulation. Cadence Virtuoso has also been used to generate the test circuits for improved layout techniques for laboratory testing.

Illustration 1: Switched Capacitor Circuit Layout

Illustration 2: Switched Capacitor Circuit Layout

Illustration 3: Switched Capacitor Circuit Schematic

Daniel Loveless

I am modeling and simulating the operation of a digital phase-locked loop circuit using the CMRF8SF IBM 130nm. The overall topology is displayed in Fig.1.

Fig.1. Schematic representation of DPLL.

The circuit consists of 4 main components: the phase-frequency detector (PFD_Buffx3), charge-pump (Chpump_2uA), low-pass filter (C LPF), and voltage-controlled oscillator (VCO_500M_mod). Fig.2 shows the schematic representation of the voltage-controlled oscillator, which consists of a string of current-starved inverters and current sources.

Fig.2. Schematic representation of voltage-controlled oscillator.

The DPLL is primarily simulated using transient simulations in order to monitor the tracking and locking periods and the output waveform. In addition, single-event transient simulations are also performed by injecting a double-exponential current pulse into the model. The tracking and locking time period is acquired by monitoring the voltage-controlled oscillator’s input voltage (Fig.3).

VinVCO (V)

Time(s)

Fig.3. Acquisition curve of the DPLL.

In addition, the output of the DPLL compared to the input clock is shown in Fig.4.

(V)

Time(s)

Fig.4. Output of the DPLL and the reference clock signal.

Jonathan Ahlbin

This is an example of Cadence Analog Environment being used to simulate a 90 nm inverter string with a pmos hit. I used a combination of transistor level inverter instances along with top-level inverter symbol instances. Using transistor level instances of inverters helps me to better control the location of the pmos and nmos hits.

This is the Analog Environment setup window that I used to perform the desired simulations. I first setup up the required models along with using stimuli to change the input values. I then chose a transient analysis that ran 8 ns and used the moderate accuracy value. As for my outputs, I selected the input and each node to analyze the effects of the pmos or nmos hits. I also chose to do an integration of the pmos/nmos hits to see how much charge is deposited.

Here is the result of performing a simulation in cadence on an inverter string with a 20 LET pmos hit.

Oluwole Amusan

The D-flip-flop and DICE Latch are two circuits being examined for Single
Event Vulnerabilities. Cadence Virtuoso Layout and Spectre allow for simulations to determine the vulnerable nodes, and the minimum amount of charge required to cause an
upset in the circuits.

Illustration 5: DFF circuit