Cadence Use in the Classroom:

• The Cadence Custom IC Design Suite of tools is extensively used in the EECE 4385 VLSI Design class (Formerly EECE 285).  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout, and functional circuit testing phases of a project.
• The Virtuoso Schematic Editor, Analog Design Environment, and Layout Suite are used.

Examples of Cadence Tool Use in Research – Team Based Design Effort with Graduate Students and Research Faculty

• In 2016, the Vanderbilt Radiation Effects Research Group and the Institute for Space and Defense Electronics setup multiple workstations dedicated to graduate student design of integrated circuits and printed circuit boards.  The area facilitates a team based approach to the design of ICs and the PCBs utilized in testing.
• The first major exercising of this team based approach design center was the design of a test chip and accompanying test boards and software to characterize the effects of radiation on circuits in a highly-scaled, FinFET technology.  The characterization circuits leverage on-chip measurement and BIST techniques.  The integrated circuit was designed with a mix of standard and custom cells with hand placement and routing using the Virtuoso Advanced Node (ICADV) suite of tools, including schematic capture and layout editor.  The Spectre Circuit simulator was extensively used for test circuit operation verification, with an without parasitic extracted elements.
• The Vanderbilt Team designed chips had 100% yield when received back from fabrication.  The IC’s were packaged at Vanderbilt and tested with a heavy-ion accelerator at Lawrence Berkeley National Laboratory, to characterize the single-event effects response of the technology and test circuits.  This design and test effort has resulted in one of the largest single-event response databases for this technology in the world, as well as many peer-reviewed journal publications that detail the test chip design and innovation, elucidated mechanisms, and novel mitigation design techniques.

Sample of 2017 – 2018 Publications that Utilized Cadence Tools in Research:

• P. Nsengiyumva et al., “Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections,” in IEEE Transactions on Nuclear Science, vol. 64, no. 1, pp. 441-448, Jan. 2017.
• T. D. Loveless et al., “Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology,” in IEEE Transactions on Nuclear Science, vol. 64, no. 1, pp. 204-211, Jan. 2017.
• R. C. Harrington et al., “Estimating Single-Event Logic Cross Sections in Advanced Technologies,” in IEEE Transactions on Nuclear Science, vol. 64, no. 8, pp. 2115-2121, Aug. 2017.
• J. S. Kauppila et al., “Exploiting Parallelism and Heterogeneity in a Radiation Effects Test Vehicle for Efficient Single-Event Characterization of Nanoscale Circuits,” in IEEE Transactions on Nuclear Science, vol. 65, no. 1, pp. 486-494, Jan. 2018.
• P. Nsengiyumva et al., “Angular Effects on Single-Event Mechanisms in Bulk FinFET Technologies,” in IEEE Transactions on Nuclear Science, vol. 65, no. 1, pp. 223-230, Jan. 2018.
• J. A. Maharrey et al., “Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques,” in IEEE Transactions on Nuclear Science, vol. 65, no. 1, pp. 362-368, Jan. 2018.
• D. R. Ball et al., “The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops,” in IEEE Transactions on Nuclear Science, vol. 65, no. 1, pp. 326-330, Jan. 2018.
• J. A. Maharrey et al., “Dual-Interlocked Logic for Single-Event Transient Mitigation,” in IEEE Transactions on Nuclear Science, vol. 65, no. 8, pp. 1872-1878, Aug. 2018.
• R. C. Harrington et al., “Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation,” in IEEE Transactions on Nuclear Science, vol. 65, no. 8, pp. 1807-1813, Aug. 2018.
• Y. Chen, “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects,” Ph. D. Dissertation, Electrical Engineering, Vanderbilt University, August 2017
• J. A. Maharrey, “Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors,” Ph. D. Dissertation, Electrical Engineering, Vanderbilt University, February 2018
• P. Nsengiyumva, “Characterization of the CMOS FinFET structure on single-event effects – basic charge collection mechanisms and soft error modes,” Ph. D. Dissertation, Electrical Engineering, Vanderbilt University, February 2018
• H. Jiang, “Design of soft-error-aware sequential circuits with power and speed optimization,” Ph. D. Dissertation, Electrical Engineering, Vanderbilt University, February 2018
• H. Zhang, “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies,” Ph. D. Dissertation, Electrical Engineering, Vanderbilt University, March 2018
• D. S. Vibbert, “An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes,” M.S. Thesis, Electrical Engineering, Vanderbilt University, August 2018

Sample of 2017-2018 Conferences Attended and Presenting Research Utilizing Cadence Tools:

• IEEE International Reliability Physics Symposium
• IEEE Nuclear and Space Radiation Effects Conference
• Government Microcircuit Applications and Critical Technology Conference
• Vanderbilt Review on Radiation Effects on Microelectronics