2016 Cadence Use in the Classroom:

• The Cadence Custom IC Design Suite of tools is extensively used in the EECE 4385 VLSI Design class (Formerly EECE 285).  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout, and functional circuit testing phases of a project.
• The Virtuoso Schematic Editor, Analog Design Environment, and Layout Suite are used.

Examples of Cadence Tool Use in Research – Establishing a Team Based Graduate Student Design Center

• In 2016, the Vanderbilt Radiation Effects Research Group and the Institute for Space and Defense Electronics setup multiple workstations dedicated to graduate student design of integrated circuits and printed circuit boards.  The area facilitates a team based approach to the design of ICs and the PCBs utilized in testing.  In 2016, the major thrust of this team based approach design center was the design of a test chip to characterize the effects of radiation on circuits in a highly-scaled, non-planer technology.  The characterization circuits leverage on-chip measurement and BIST techniques.  The integrated circuit was designed using the Virtuoso Advanced Node (ICADV) suite of tools, including schematic capture and layout editor.

A Ph.D. student in the Vanderbilt University Radiation Effects Research Group utilizes the Cadence ICADV suite of tools to design an on-chip measurement circuit in a highly-scaled, non-planer technology.

Sample of 2015 – 2016 Publications that Utilized Cadence Tools in Research:

• Content to be added soon

Sample of 2016 Conferences Attended and Presenting Research Utilizing Cadence Tools:

• IEEE International Reliability Physics Symposium
• IEEE Nuclear and Space Radiation Effects Conference
• Government Microcircuit Applications and Critical Technology Conference