Radiation Effects and Reliability Group

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2014 Research Projects Using Cadence Tools

2014 Cadence Use in the Classroom:

  • The Cadence Custom IC Design Suite of tools is extensively used in the EECE 285 VLSI Design class.  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout, and functional circuit testing phases of a project.
  • The Virtuoso Schematic Editor, Analog Design Environment, and Layout Suite are used.

2014 Examples of Cadence Use in Research:

Sample of 2013 – 2014 Publications that Utilized Cadence Tools in Research:

  • Diggins, Z.J.; Gaspard, N.J.; Mahatme, N.N.; Jagannathan, S.; Loveless, T.D.; Reece, T.R.; Bhuva, B.L.; Witulski, AF.; Massengill, L.W.; Wen, S.-J.; Wong, R., “Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes,” Nuclear Science, IEEE Transactions on , vol.60, no.6, pp.4394,4398, Dec. 2013
  • Gaspard, N.J.; Jagannathan, S.; Diggins, Z.J.; King, M.P.; Wen, S.-J.; Wong, R.; Loveless, T.D.; Lilja, K.; Bounasser, M.; Reece, T.; Witulski, AF.; Holman, W.T.; Bhuva, B.L.; Massengill, L.W., “Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections,” Nuclear Science, IEEE Transactions on , vol.60, no.6, pp.4368,4373, Dec. 2013
  • Gaspard, N.; Jagannathan, S.; Diggins, Z.J.; Mahatme, N.N.; Loveless, T.D.; Bhuva, B.L.; Massengill, L.W.; Holman, W.T.; Narasimham, B.; Oates, A; Marcoux, P.; Tam, N.; Vilchis, M.; Wen, S.-J.; Wong, R.; Xu, Y.Z., “Soft error rate comparison of various hardened and non-hardened flip-flops at 28-nm node,” Reliability Physics Symposium, 2014 IEEE International , vol., no., pp.SE.5.1,SE.5.5, 1-5 June 2014
  • Gaspard, N.; Jagannathan, S.; Diggins, Z.; Kauppila, AV.; Loveless, T.D.; Kauppila, J.S.; Bhuva, B.L.; Massengill, L.W.; Holman, W.T.; Oates, AS.; Fang, Y.; Wen, S.; Wong, R., “Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS,” Reliability Physics Symposium (IRPS), 2013 IEEE International , vol., no., pp.SE.7.1,SE.7.3, 14-18 April 2013
  • Gaspard, N.; Jagannathan, S.; Diggins, Z.; McCurdy, M.; Loveless, T.D.; Bhuva, B.L.; Massengill, L.W.; Holman, W.T.; Oates, T.S.; Fang, Y.-P.; Wen, S.-J.; Wong, R.; Lilja, K.; Bounasser, M., “Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS,” Reliability Physics Symposium (IRPS), 2013 IEEE International , vol., no., pp.SE.6.1,SE.6.5, 14-18 April 2013
  • Kauppila, J.S.; Loveless, T.D.; Quinn, R.C.; Maharrey, J.A; Alles, M.L.; McCurdy, M.W.; Reed, R.A; Bhuva, B.L.; Massengill, L.W.; Lilja, K., “Utilizing device stacking for area efficient hardened SOI flip-flop designs,” Reliability Physics Symposium, 2014 IEEE International , vol., no., pp.SE.4.1,SE.4.7, 1-5 June 2014
Sample of 2014 Conferences Attended and Presenting Research Utilizing Cadence Tools:
  • IEEE International Reliability Physics Symposium
  • IEEE Nuclear and Space Radiation Effects Conference
  • Single Event Effects Symposium
  • Conference on the Application of Accelerators in Research and Industry
  • Hardened Electronics and Radiation Technology Conference