2013 Cadence Use in the Classroom:

• The Cadence Custom IC Design Suite of tools is extensively used in the EECE 285 VLSI Design class.  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout, and functional circuit testing phases of a project.
• The Virtuoso Schematic Editor, Analog Design Environment, and Layout Suite are used.

2013 Examples of Cadence Use in Research:

• Design, Test, and Characterization of a Circuit for Single-Event Transient Pulse-Width On-Chip Measurement in Advanced CMOS Technologies
• Virtuoso Schematic Editor & Layout Suite
• Analog Design Environment
• Spectre & UltraSim Circuit Simulators
• Using Cadence Tools for RF Test Chip Design, Characterization, and Degraded Performance Model Development, with Application to a 20+GHz Voltage Controlled Oscillator
• Virtuoso Schematic Editor & Layout Suite
• Analog Design Environment
• Spectre & Spectre RF Circuit Simulators

Sample of 2012 – 2013 Publications that Utilized Cadence Tools in Research:

• Loveless, T.D.; Kauppila, J.S.; Jagannathan, S.; Ball, D.R.; Rowe, J.D.; Gaspard, N.J.; Atkinson, N.M.; Blaine, R.W.; Reece, T.R.; Ahlbin, J.R.; Haeffner, T.D.; Alles, M.L.; Holman, W.T.; Bhuva, B.L.; Massengill, L.W., “On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology,” Nuclear Science, IEEE Transactions on , vol.59, no.6, pp.2748,2755, Dec. 2012
  doi: 10.1109/TNS.2012.2218257
• Blaine, R.W.; Atkinson, N.M.; Kauppila, J.S.; Loveless, T.D.; Armstrong, S.E.; Holman, W.T.; Massengill, L.W., “Single-Event-Hardened CMOS Operational Amplifier Design,” Nuclear Science, IEEE Transactions on , vol.59, no.4, pp.803,810, Aug. 2012
  doi: 10.1109/TNS.2012.2200502
• Blaine, R.W.; Atkinson, N.M.; Kauppila, J.S.; Armstrong, S.E.; Hooten, N.C.; Warner, J.H.; Holman, W.T.; Massengill, L.W., “Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design,” Nuclear Science, IEEE Transactions on , vol.59, no.6, pp.2867,2871, Dec. 2012
  doi: 10.1109/TNS.2012.2222441
• Atkinson, N. M.; Blaine, R. W.; Kauppila, J. S.; Armstrong, S. E.; Loveless, T. D.; Hooten, N. C.; Holman, W. T.; Massengill, L. W.; Warner, J. H., “RHBD Technique for Single-Event Charge Cancellation in Folded-Cascode Amplifiers,” Nuclear Science, IEEE Transactions on , vol.PP, no.99, pp.1,6, 0
  doi: 10.1109/TNS.2013.2240316
• Armstrong, S.E.; Blaine, R.W.; Holman, W.T.; Massengill, L.W., “Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices,” Nuclear Science, IEEE Transactions on , vol.59, no.4, pp.1027,1033, Aug. 2012
  doi: 10.1109/TNS.2012.2194166
• Sarah has graduated with her Ph.D. and now works with NAVSEA Crane in Crane, IN
• Kauppila, A.V.; Bhuva, B.L.; Loveless, T.D.; Jagannathan, S.; Gaspard, N.J.; Kauppila, J.S.; Massengill, L.W.; Wen, S. -J; Wong, R.; Vaughn, G.L.; Holman, W.T., “Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops,” Nuclear Science, IEEE Transactions on , vol.59, no.6, pp.2651,2657, Dec. 2012
  doi: 10.1109/TNS.2012.2224136
• Amy has graduated with her Ph.D. and now works with Infoworks, Inc. in Nashville, TN
• Ahlbin, J.R.; Hooten, N.C.; Gadlage, M.J.; Warner, J.H.; Buchner, S.P.; McMorrow, D.; Massengill, L.W., “Identification of pulse quenching enhanced layouts with subbandgap laser-induced single-event effects,” Reliability Physics Symposium (IRPS), 2013 IEEE International , vol., no., pp.6C.2.1,6C.2.6, 14-18 April 2013
  doi: 10.1109/IRPS.2013.6532052
• Jon has graduated with his Ph.D. and now works with ISI, USC in Arlington, VA

Sample of 2013 Conference Presentations that Utilized Cadence Tools in Research:

• “The Quad-Path Hardening Technique for Switched-Capacitor Circuits”, N. M. Atkinson, W. T. Holman, J. S. Kauppila, T. D. Loveless, N. C. Hooten, L. W. Massengill, Vanderbilt University; J. H. Warner, Naval Research Laboratory – Presented at IEEE NSREC 2013
• “A New Error Correction Circuit for Delay Locked Loops”, P. Maillard, T. W. Holman, T. D. Loveless, L. W. Massengill, Vanderbilt University – Presented at IEEE NSREC 2013
• “SET Pulse Width Trends in 45 nm and 32 nm SOI”, J. Maharrey, R. C. Quinn, S. Jagannathan, N. M. Atkinson, N. J. Gaspard, E. X. Zhang, T. D. Loveless, J. S. Kauppila, W. T. Holman, B. L. Bhuva, L. W. Massengill, Vanderbilt University – Presented at IEEE NSREC 2013
• “Sensitivity of High-Frequency RF Circuits to TID Degradation”, S. Jagannathan, D. T. Loveless, E. X. Zhang, D. M. Fleetwood, R. D. Schimpf, T. D. Haeffner, J. S. Kauppila, N. Mahatme, B. L. Bhuva, M. L. Alles, W. T. Holman, A. F. Witulski, L. W. Massengill, Vanderbilt University – Presented at IEEE NSREC 2013