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USING CADENCE TOOLS FOR STATISTICAL FAULT INECTION AND ANALYSIS AT THE REGISTER TRANSFER LEVEL USING THE VERILOG PROCEDURAL INTERFACE

By Corey Toomey

 

Introduction

An approach has been developed to determine the architectural vulnerability factor of a design and its sub-modules along with other metrics including error latency and error persistence. The design used as a test bed for this thesis was an ASIC design with 1.1 million register elements. This design is written in verilog at the register transfer level. The tools used for fault injection and error detection were written in C/C++ and used the verilog procedural interface. It was found that by using the methodology laid out in this thesis, that a designer could use the data found during simulation to rank the sub-modules of a design by a vulnerability factor. A designer could then use this ranking to selectively harden the design.

Single Event Simulations

A process seen in figure 1 was used to run single event simulations on the ASIC described previously. The blue boxes were supplied by the design, the yellow boxes were modules written using the verilog procedural interface and used to inject faults and detect errors. The white box represents the verilog simulator, which in this case was NCVerilog.

Fig. 1 – Block diagram of proposed methodology

Approximately 1400 simulations were carried out each one representing a single fault injection and possible error. Figure 2 represents one interpretation of the data obtained from those simulations. The yellow represents the number of register bits in each sub-module. The red represents the number of faults injected, and the blue represents the number of errors detected.

Fig. 2 – Sub-Module data for single-event simulations

Figure 3 represents another way to interpret the raw data. This chart represents the architectural vulnerability factor versus number of simulations. While it is approaching 5 percent, it is clear that more simulations are needed to begin to make the line saturate single number.

Fig. 3 – AVF versus number of fault injections