Radiation Effects and Reliability Group

Home » Cadence University Program » 2010 research projects using Cadence tools » A Hardened-by-Design Bias Circuit Utilizing Sensitive Node Active Charge Cancellation (SNACC)

A Hardened-by-Design Bias Circuit Utilizing Sensitive Node Active Charge Cancellation (SNACC)

 

R. W. Blaine, S. E. Armstrong, B. D. Olson, W. T. Holman, J. S. Kauppila, and

L. W. Massengill

 

I. Background

Bias circuitry can be particularly sensitive to single events (SE).  Previous work has shown that this phenomena can produce extreme circuit behaviors [1,2,3]. In these works this behavior manifested itself in three different ways: a near doubling in operation frequency in the output of a voltage-controlled oscillator, millisecond-long transients on the output of a LM6144 operational amplifier, and transients in an analog-to-digital converter that caused thousands of missed samples.

Previous work presented a radiation-hardened-by-design (RHBD) technique for bias circuitry that took advantage of the multi-node charge collection mechanisms and employed them through a balancing and mirroring circuit topology to mitigate the effects of a single event strike to reduce voltage transients. This technique called sensitive node active charge cancellation (SNACC) was shown to be greatly more effective than a capacitive hardening technique when simulated on a basic bias circuit, a diode and resistor [4].  This work will apply this tecnique to a bootstrap current source topology to show SNACC’s effectiveness on a more advanced circuit.

 

II. Circuit Design

Fig.1a shows the bootstrap current source studied in this work.  The circuit was designed using the IBM 90 nm process design kit PDK with 150 x 1 m PMOS and 60 x 1 m NMOS devices providing a reference current of 26 A.  The node between the drains of device M2 and device M4 is the most sensitive to SE strikes.  Fig. 1b shows a schematic of the proposed hardening technique with the relative transistor sizes labeled.  The additional circuitry in Fig. 1b does not change the overall operation of the original circuit in any way.  In fact during normal operation all the added devices are biased off, therefore drawing no extra power.

Fig 1. (a) Circuit diagram of the bootstrap current source.  The startup circuitry is highlighted gray and has no impact during normal circuit operation. (b) The SNACC hardening technique applied to the node shared between M2 and M4 with the W/L ratios labeled

 

 

 

 

The proposed bias circuit of Fig. 1b uses the building block of Fig. 1a.  The key to successful implementation of this design involves a specific layout technique in which transistors M12 an M7 are laid out as two sets of transistors in parallel. One set of M12’s unit cell transistors are interleaved with device M11 and the other set with device M4, thus allowing maximum common charge collection of a SE strike on devices M11 and M12 or on devices M4 and M12. The two sets of interleaved PMOS devices are placed in separate wells and separated by the NMOS devices to prevent multi-node charge collection occurring between devices M11 and M4. The NMOS devices, M2 and M8 are interleaved in the same fashion as the PMOS devices with M7.

A voltage transient can occur if device M4 sources or M2 sinks current from a SE strike.  If device M12 or M7 also collects charge, an equal current will ideally be sourced or sunk through the current mirror of M8 and M9 or M10 and M11, resulting in no net change at the bias node, thus mitigating the transient. The same mitigation mechanism is present for PMOS devices M11 and M12, and also for NMOS devices M7 and M8. There is no impact on the circuit if a SE strike occurs on devices M10 or M9.

 

III. Model and Simulation Results

The circuits of Fig. 1 were designed and laid out in Cadence using the IBM 90-nm process design kit (PDK). The circuit from Fig. 1a establishes a baseline bias circuit without hardening. A Cadence Spectre circuit model was recently developed for the IBM 90-nm PDK that captures the dynamic charge collection interactions represented in a 3-D technology computer aided design (TCAD) [5]. These three circuits were simulated with this model in Cadence Spectre simulations in order to determine the effectiveness of the hardening technique. The simulations characterize a SE strike on every transistor in the RHBD technique varying the strike’s linear energy transfer (LET) from 10 – 40 MeV-cm2/mg in increments of 10 MeV-cm2/mg, for both normal incidence and 60 degree strikes.

Fig 2. Sample results for voltage perturbations measured on a mirrored transistor with a resistor to establish a VREF following SET strikes on device M4 with varying LET.  On the left are the magnitude of the transients and on the right the durations.

 

 

 

 

Fig. 2 demonstrates the merit of the SNACC technique.  Similar results were recorded for normal strikes on M4 as well as for normal and angled strikes to M2.  It is important to note that this technique provided additional SE hardness to two separate sensitive junctions.

 

III. Conclusions

These simulations have shown the use of SNACC can minimize the effects of a SE from both a amplitude and duration stand point on a critical node.  The SNACC technique is available in any commercial bulk process and causes very few design penalties.  Additional area and sensitive devices are added and will be discussed in further detail in the full paper.

 

IV. References

[1] T. D. Loveless et al. “Modeling and Mitigating Single-Events Transients in Voltage-Controlled Oscillators” IEEE Trans. Nucl. Sci. vol. 54 no. 6, 2561 (2007)

[2] Y. Boulghassoul et al. “Investigation of Millisecond-Log Analog Single-Event Transients in the LM6144 Op Amp” IEEE Trans. Nucl. Sci. vol. 51 no 6, 3529 (2004)

[3] Kirby Kruckmeyer et al., “Use of Code Error and Beat Frequency Test Method to Identify Single Event Upset Sensitive Circuits in a 1 GHz Analog to Digital Converter” IEEE TNS, 2008

[4] R.W. Blaine, et al. “SNACC: Sensitive Node Active Charge Cancellation for RHBD Circuits” Accepted for presentation at 2010 Radiation and Effects on Components and Systems Conference, Langenfeld, Austria, September, 2010

[5] Jeffrey S. Kauppila et al. “A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit” IEEE Trans. Nucl. Sci. vol. 56 no. 6, 3152 (2009)