By Matthew Gadlage

 

Introduction

 

A single event transient in a digital circuit can be induced by an energetic particle in combinational logic schematically located between storage cells.  This transient can propagate through the combinational logic and arrive at the input of a latch on the latching edge of the clock.  The wider the transient width, the greater probability it has of arriving on the latching edge of the clock.  Since the probability of latching a digital SET as an error is directly proportional to its pulse width, it is imperative that characterization of SET pulse widths be carried out for each technology generation.

 

Circuit Design and Layout

 

Using the Cadence Spectre tool, an SET measurement circuit in a 65-nm bulk CMOS technology node was designed and simulated.  The Cadence Virtuoso layout tool was used to generate the fabricated circuit layout. The test circuit is able to measure the SET pulse widths in terms of inverter delays. The circuit is based on the principle that within an inverter chain, an SET pulse will affect a number of inverters that is proportional to the pulse width [1]. The test circuit consists of a target circuit (used to generate SETs) followed by an 80-stage measurement circuit. The 80 stages are connected to latches that store the number of inverters affected by each SET. An SET pulse detection circuit is used to trigger the latches. The measurement circuit essentially forms a series of latches that freeze the SET pulse for measurement (Fig. 1). With the individual inverter stage delay of about 25 ps and 80 latch stages, this circuit allows measurement of SET pulses ranging from 25 ps to 2 ns with a 12.5 ns measurement resolution [2-4].

 

 

1.)1000 inverter chain with the PMOS devices in the same N-well.

 

 

 

 

 

 

 

 

 

 

Fig. 2:  Inverter Chain in Which the PMOS Devices are in the Same N-Well

 

 

 

1.)1000 inverter chain with the PMOS devices in separate N-wells.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig. 3:  Inverter Chain in Which the PMOS Devices are in Different N-Wells

 

2.)Ten 100 inverter chains (with the PMOS devices in the same N-Well) “OR”-ed together to form one single output.

 

3.)NOR chain with inverters in which only the PMOS device will be sensitive to SETs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig. 4: Schematic of the NHIT Circuit

 

4.)NAND chain with inverters in which only the NMOS device will be sensitive to SETs.

 

 

 

 

 

 

 

 

 

Fig. 5: Schematic of the PHIT Circuit

 

 

References

 

[1]B. Narasimham, V. Ramachandran, B. L. Bhuva, R. D. Schrimpf, A. F. Witulski, W. T. Holman, L. W. Massengill, J. D. Black, W. H. Robinson, D. McMorrow, “On-chip characterization of single event transient pulse widths”, IEEE Trans. on Dev. and Mat. Rel., vol. 6, p. 542-549, 2006.

[2]B. Narasimham, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, M. J. Gadlage, O. A. Amusan, W. T. Holman, A. F. Witulski, W. H. Robinson, J. D. Black, J. M. Benedetto, and P. H. Eaton, “Characterization of digital single event transient pulse-widths in 130-nm and 90-nm CMOS technologies,”, IEEE Trans. on Nucl. Sci., vol. 54, no. 6, p. 2506-2511, 2007.

[3]B. Narasimham, M. J. Gadlage, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, W. T. Holman, A. F. Witulski, X. Zhu, A. Balasubramanian, and S. A. Wender, “Neutron and alpha particle-induced transients in 90 nm technology,” IEEE International Reliability Physics Symposium, p.478-481, April 27 2008 – May 1 2008.

[4]M. J. Gadlage, R. D. Schrimpf, B. Narasimham, J. A. Pellish, K. M. Warren, R. A. Reed, R.A. Weller, B. L. Bhuva, L. W. Massengill, and X. Zhu, “Assessing alpha particle-induced single event transient vulnerability in a 90-nm CMOS technology,” IEEE Electron Device Letters, vol. 29, no. 6, p. 638-640, June 2008.