Introduction

In modern integrated circuit processes, high-performance mixed-signal designs commonly use differential topologies and switched-capacitor input/feedback networks to obtain greater dynamic range, better noise rejection, and improved component matching to their single-ended, continuous-time counterparts [1].  For example, high-speed data converters make extensive use of differential switched-capacitor topologies.  Unfortunately, switched-capacitor circuit topologies typically exhibit much greater single-event vulnerability than their continuous-time counterparts due to the presence of floating nodes in the switched-capacitor network [2, 3].  Floating nodes have no charge dissipation path, so charge deposited on a floating capacitor by a single-event effect will persist until the next clock phase.  In contrast, given sufficient time and restoring currents, a node in a continuous-time circuit can dissipate collected charge, but at the cost of slower speed and higher power dissipation.  Consequently, it is not practical to harden modern mixed-signal circuit designs against single-event effects simply by migrating to continuous-time topologies.

 

Switched-capacitor comparators are commonly used in a variety of mixed-signal applications.  These circuits compare an input voltage to a reference voltage and latch a logic ‘1’ or ‘0’ at the output depending on whether the input voltage is higher or lower than the reference voltage.  It is essential that valid comparator operation be ensured even in the presence of single-events.  For example, in a pipelined analog-to-digital converter (ADC) a false comparison in the first stage may result in an erroneous value for the most significant bit (MSB).  By applying a modification of a design technique developed in [2] to a high-performance comparator, the vulnerability of floating nodes in the switched-capacitor network can be dramatically reduced.

 

Design

 

Cadence Spectre was used to implement and evaluate a dual path radiation-hardened by design (RHBD) comparator.  The RHBD technique provides a simple but effective means of hardening the floating input nodes for a switched-capacitor comparator [4].  A simplified circuit diagram of both baseline and RHBD comparator are shown in Fig. 1 and Fig. 2.

 

 

 

Results

 

By splitting up the input nodes into separate parallel signal paths, a dramatic improvement in single-event hardness is observed, as shown in Fig. 3 and Fig. 4 [4].  The differential input voltage is shown on the x-axis while the deposited charge is shown on the y-axis.  The dark region indicates the charge deposited onto the floating node is sufficient to force an erroneous output.  These results indicate that the dual signal path RHBD technique should be extremely effective at reducing single-event errors for a broad range of switched-capacitor circuits, with or without feedback.

 

 

 

Layout

 

Cadence Virtuoso Layout XL has been used to design layouts of the comparator, and is shown in Fig. 5 and Fig. 6.  Fabricated comparator devices will support this work by providing experimental verification of the simulation results.

 

 

 

References

[1] P. E. Allen and E. Sanchez-Sinencio, Switched-Capacitor Circuits. New York : Van Nostrand Reinhold, 1984.

[2] P. R. Fleming, B. D. Olson, W. T. Holman, B. L. Bhuva, and L.W. Massengill, “Design Technique for Mitigation of Soft-Errors in Differential Switched-Capacitor Circuits,” currently in press for IEEE Transactions on Circuits and Systems II.

[3] P. R. Fleming, An RHBD Technique to improve the single-event vulnerability of switched-capacitor differential circuits, MS Thesis, Vanderbilt University, 2007.

[4] B. D. Olson, W. T. Holman, L. W. Massengill, B. L. Bhuva, and P. R. Fleming, “Single-Event Effect Mitigation in Switched-Capacitor Comparator Designs,” presented at the 2008 IEEE Nuclear and Space Radiation Effects Conference and has been submitted for publication in IEEE Trans. Nucl. Sci.