By: Pierre Maillard

The main goals of this project are to understand and quantify single-event transients (SET) in delay-locked loop (DLL) circuits and to develop radiation-hardened-by-design (RHBD) strategies for SET mitigation in DLLs. Using the Cadence software package we have developed we developed DLLs in 90 nm IBM technology. Fig. 1 illustrates the general block diagram of the DLL circuits composed by four main blocks: the phase- detector (PD), charge pump (CP), low-pass filter (LPF), and voltage-controlled delay line (VCDL). Buffers were included subsequent to the VCO module to account for loading effects. The DLL circuits 90nm were designed to achieve a center frequency of range between 500 MHz and approximately 1.5 GHz which represent the operating range of the DLL at 1GHz.

Fig. 1. General block diagram of the DLL : Self correcting phase detector (PD), charge pump (CP), low-pass filter (LPF), voltage-controlled delay line (VCDL)

 

The PHASE DETECTOR

 

The phase detector is the most important component of the CDR design. It compares the phases of the two high frequency signals, and generates the control signals that drive the VCDL clock. The desired accuracy, the frequency of operation, together with the random and noisy nature of the input, makes this block difficult to design.

The Hogge Phase detector:

Derived from the bang-bang architectures, the linear PDs are classified by the control voltages linearly proportional to the amount of phase difference between the input and the reference. The goal is to accurately present the amount of adjustment to the VCDL control voltage. One of the earliest examples is the Hogge architecture. Its architecture and waveform sample is shown in Figure 1. The input data is sampled at the rising edge of the clock signal by the first flip-flop. The second flip-flop samples the output of the first flip-flop at the falling edge of the clock. Then the three sample points are passed to the two XOR gates to generate the control signals down and up. The phase error is shown in the difference between the duty cycles of down and up. Lock occurs when the clock signal rises at the middle of the data pulse, so that Down and Up have equal duty cycles. The control mechanism is improved because Down and Up express the phase difference linearly. However, they still toggle on and off alternately at lock. Therefore, rippling is still a problem in this design. I designed the Hogge PD using cadence virtuoso and simulated the circuits using the analog environment tools.

 

 

 

Fig. 2. Hogge PD and its sample waveform

 

Case when Loop is locked:

 

Fig. 3. Simulation of Hogge PD (Loop Locked)

 

 

According to the theory Lock occurs when the clock signal rises at the middle of the data pulse, so that UP and DOWN have equal duty cycles and DOWN is in phase with the reference clock. In the simulation results above we can see that the outputs UP and DOWN have the same duty cycle (same period ~ 2ns), but because of the non ideal behavior of the latches we got a little shift time between the outputs and the reference clock. However we can conclude that the results fit well with the requirements.

 

Case 2: Data and ref_clock in phase:

 

Figure 4: simulation Hogge PD (Data clock in phase)

 

This simulation represents the case when there is no phase difference between the Data and the ref_clock.

In the theory the output UP is supposed to be null, and DOWN in phase with the reference clock, but when I simulated this case with my designed phase detector it appear that the output UP generated a signal wider than the DOWN output (2ns UP pulse vs. 1ns for DOWN), this phenomenon is due to the fact that the D flip flop output is generated one clock period after the first rising edge. I don’t know yet if this case will be a problem or not for the DLL behavior, however in the papers i read, the case when the data and the clock are in phase for a hogge PD as never been referred;

Therefore for more cautiousness, I decide to design another Phase detector more used in recent DLL, the Dynamic Phase detector.

 

This work shows that the Cadence software package can be used to accurately design high-speed mixed-signal electronics like Delay locked loop. In a close future the cadence tools will be use to predicted the error response of the DLL circuits in a radiation environment incorporating both hardened and un-hardened sub-circuits.