By Oluwole Amusan

Introduction

Charge sharing is due to multiple node charge collection from a single ion strike. Charge sharing was first observed in SRAM designs [1], and recent work [2] – [6] has shown charge sharing to be a major Single Event Effect (SEE) for deep-submicron technologies due to the reduced spacing of circuit nodes with scaling technology. Charge sharing is expected to exacerbate with scaling technology due to scaling trends such as reduced nodal charge, higher packing densities, and reduced spacing between devices; hence there is a growing need to quantify charge sharing for advanced technologies. As the charge collection mechanisms associated with charge sharing (i. e., drift, diffusion and bipolar amplification [7]) can vary from technology to technology and from process to process, each process may need to be individually calibrated and evaluated. This summary discusses the use of the Cadence tools in designing the charge sharing measurement circuit and shows the layout of the circuit for a 90 nm process fabricated through the MOSIS foundry.

Circuit Design and Layout

Using the Cadence Spectre tool, a charge sharing measurement circuit was designed and simulated, the Cadence Virtuoso layout tool was used to generate the fabricated circuit layout. The measurement circuit as shown in Fig. 1 measures the amount of charge collected by a node based on the equation: ΔQ = Cpassive * ΔV (1) Where Cpassive is the nodal capacitance and ΔV is the change in the nodal voltage. The Cpassive is connected to the drain area of the passive transistor as shown in Fig. 1. Initially, Cpassive is charged to a known voltage (or discharged to a known voltage) and cut-off from the rest of the circuit by turning off all transistors connected to the hit node. After the SE hit, the sense amplifier is used to compare hit node voltage with reference voltage to estimate the hit node voltage. Care must be taken to measure the node voltage soon after the hit to reduce any leakage. As all circuit nodes have leakage, measurement taken after a long time after the SE hit will not yield correct results. As this is part of an on-going research, the design of the Sense Amplifier (schematic shown in Fig. 2) and the layout of the measurement circuit (shown in Fig. 3) will not discussed.

Fig. 1. Measurement circuit for passive NMOS device determines the amount of charge collected due to charge sharing.

Fig. 2. Design of Sense Amplifier circuit using Cadence Spectre tool.

Fig. 3. Layout of charge sharing measurement circuit using the Cadence Virtuoso layout tool.
REFERENCES
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[3] L. W. Massengill, “Scaling vs. SEE Mitigation,” presented at the Single Event Effects (SEE) Symposium 2006 , Long Beach, CA. April 2006.
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