By: Daniel Loveless

The main goals of this project are to understand and quantify single-event transients (SET) in phase-locked loop (PLL) circuits and to develop radiation-hardened-by-design (RHBD) strategies for SET mitigation in PLLs. Using the Cadence software package we have developed numerous phase-locked loop topologies in 130 nm and 90 nm technology nodes. Fig. 1 illustrates the general block diagram of the PLL circuits consisting of four primary components: the phase-frequency detector (PFD), charge pump (CP), low-pass filter (LPF), and voltage-controlled oscillator (VCO). Buffers were included subsequent to the VCO module to account for loading effects. The PLL circuits in a 130 nm technology node were designed to achieve a center frequency of 400 MHz and a maximum frequency of approximately 1 GHz.

Fig. 1. General block diagram of the PLL circuit including the phase-frequency detector (PFD), charge pump (CP), low-pass filter (LPF), voltage-controlled oscillator (VCO), and output buffers.

When analyzing the electrical performance of the PLL, the input of the VCO (VinVCO) can be a useful metric. Fig. 2 shows a simulation of the acquisition curve of the PLL for 700 MHz operation. The acquisition or tracking period denotes the time period when VoutVCO is lagging (leading) in frequency and phase when compared to the input reference signal, VREF. The voltage at the input of the VCO changes with every clock cycle as the PFD continues to compare the leading edges of the signals, and the CP continues to source (sink) current to (from) the LPF. Once the phase and frequency of VoutVCO and VREF are identical, VinVCO should ideally remain constant indefinitely as the PLL is in the lock state.

Fig. 2. Acquisition and lock curve: VinVCO vs. time for 700 MHz operation.

Additionally, we have developed the layout of the circuits using Virtuoso, fabricated, and tested the devices in 130 nm. Fig. 3 illustrates the measured transfer characteristics of the VCO circuits within each PLL, indicating the PLL operating frequency range. An approximate 2x decrease in the output frequency of the measured devices over the simulated devices occurred.

Fig. 3. Measured transfer curves of the VCO circuits. The center frequencies were approximately 200 MHz and the maximum frequencies were between 500 MHz and 600 MHz. The PLLs’ locking ranges were between approximately 40 MHz and 350 MHz.

In analyzing PLL circuits for SET sensitivity, PLL circuits incorporating a novel, SE-hardened charge pump were designed and fabricated in a 130 nm technology. Experimental testing was performed using two-photon absorption (TPA) on the PLL circuits for single-event-upset (SEU) mapping and SET error signature characterization. SEU mapping was used to quantify the vulnerable areas of each PLL sub-circuit, indicating an approximate 99 % reduction in the cross-section of the radiation-hardened-by-design (RHBD) charge pump over the conventional design. Second, analysis of the measured PLL output error signatures was used to quantify the relative hardness of PLL circuits implementing a voltage-based charge pump (V-CP) over a design implementing a conventional current-based charge pump (CP), demonstrating 2.3 orders of magnitude improvement in SE tolerance. Additionally, SET simulations using the Cadence software package were performed on the circuits and compared to the experimental results in Fig. 4.

Fig. 4. (a) Maximum number of erroneous clock pulses versus frequency for laser strikes in various PLL sub-circuits. A maximum of 2.3 orders of magnitude improvement was achieved by the RHBD charge pump over the conventional design. The incident laser energy was 30 nJ. (b) The maximum phase displacement vs. frequency for SE strikes depositing 500 fC of charge in the CP, VCO, and V-CP. At least 2 orders of magnitude improvement is achieved by the V-CP over the CP.

Fig. 4(a) illustrates the maximum number of erroneous clock pulses (missing or additional clock pulses) in the output of the PLL circuits following a laser strike in the various PLL sub-circuits (conventional charge pump, voltage-controlled oscillator, and RHBD charge pump). A maximum of 2.3 orders of magnitude improvement was achieved by the RHBD charge pump over the conventional design. Similarly, Fig. 4(b) illustrates the phase displacement in the output of the PLL circuits following a simulated single-event strike in the various PLL sub-circuits. At least 2π radians of phase displacement are required to get 1 erroneous clock pulse. In agreement with the experimental results shown in Fig. 4(a), the Cadence simulations indicate an approximate 2.3 orders of magnitude improvement in the PLL’s output phase displacement following simulated ion strikes in the RHBD charge pump (V-CP) over the conventional charge pump (CP).

This work shows that the Cadence software package can be used to accurately design high-speed mixed-signal electronics such as PLLs. Additionally, simulations accurately predicted the error response of the PLL circuits in a radiation environment incorporating both hardened and un-hardened sub-circuits.